The present invention relates generally to semiconductor device processing and, more particularly, to a method for reducing shallow trench isolation consumption in semiconductor devices.
In typical semiconductor device manufacturing processes, trench isolation, particularly shallow trench isolation (STI), is used to replace conventional local oxidation of silicon (LOCOS). An STI region is generally composed of a pure oxide material, such as a high-density plasma (HDP) oxide or a plasma tetraethyl orthosilicate (TEOS). Since the STI trench formation and STI fill processes are performed at the beginning of the chip manufacturing process, the STI oxide encounters many subsequent wet etch processing steps (e.g., with dilute hydrofluoric acid (HF) or buffered HF), as well as dry etching steps (e.g., reactive ion etching (RIE)). Thus, as a normal part of the fabrication process leading to the final device, at least a portion of the STI oxide will be etched away. This leads to a change in the height of the STI oxide as compared with the rest of the silicon active area (both of which exhibit various height changes as the silicon wafer proceeds through the chip manufacturing process).
Because there are many etch steps between STI formation and polysilicon deposition, and because each etching step has individual variables associated therewith, there is often a lack of control over the amount of etching the STI actually undergoes. In wet chemical baths, for example, the HF concentration is known to change over the life of the bath. Also, depending on the application technique used to administer the HF, there may also be variations of the etching rate on the wafer itself. Similarly, RIE tools, which typically process one wafer at a time, have well known across-wafer variations and wafer-to-wafer variations.
One way to reduce the erosion of the STI region is simply to eliminate as many wet and dry etch steps as possible between STI formation and deposition. For example, elimination of the sacrificial oxidation and oxide strip steps used to condition the active area surface provides some simplification. However, this approach can only be taken so far, as some of these steps may be necessary to create the final circuit and achieve necessary yield. Another way to reduce STI erosion is to reduce the amount of exposure to chemical etchants used in each of the required etch steps. Likewise, this approach is problematic since the etchant steps are often made intentionally long in order to remove particulates, remedy inconsistent oxide thicknesses or create hydrogen-terminated surfaces for subsequent processes.
Other efforts have been made to form caps over the STI material in order to inhibit STI erosion during subsequent etching steps used to form the active areas. For example, U.S. Pat. No. 6,146,970 to Witek, et al. describes the use of a silicon nitride or nitrogen-rich silicon oxynitride layer for capping an oxide STI material such as TEOS. However, the Witek, et al. bilayer approach adds significant cost and process complexity to the formation of STI. In particular, Witek, et al. use two separate liner processes, two separate deposition processes and two separate CMP processes.
In this regard, acceptable solutions to the erosion of STI are preferably simple and cost-effective. In addition to exhibiting simplicity and low cost, acceptable solutions should have sufficient robustness such that it is unnecessary to constrain other process variables simply to control STI height. At the same time, such solutions must preferably fit within existing processes so as to avoid affecting product yield and cost.
STI consumption is a particularly significant challenge for state of the art, high performance CMOS. One requirement is that STI to active area step height be minimal (e.g., less than about 20 nm), just prior to gate poly deposition. If this requirement is not met then the gate stack lithography may be compromised. The step height requirement is even more stringent for ultra-thin Si channel devices. If the STI is recessed below the active area, then a reentrant structure is formed which can trap gate poly that cannot be removed by the gate stack etch. In the case of process flows using raised source/drain diffusions, the STI to active area step height should still be slightly positive. The slightly positive step with the STI is higher is needed to prevent lateral growth of the raised source/drain regions which can cause shorting for minimum-spaced active area features.
In the case of bulk devices, the STI/active area step height must not be lower than the source drain junction at the time of silicidation. High off current can result from silicide bridging from the source drain to the well. Accordingly, for these and other reasons, a need exists for an effective method for reducing STI consumption.